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JEFFRY A. DECOLA

CONTROL AN FPGA VIA A RASPI AND WEB SERVER

GITHUB REPO

CONTROL AN 8-BIT MICROPROCESSOR I DESIGNED

Code written in php, js, go & verilog

TRY IT - CLICK COMPUTE

ADD 0011
SUBTRACT 0011
DIVIDE 0110
MULTIPLY 1100

OPCODE

DATA_IN_A

DATA_IN_B

CLICK HERE

DATA_OUT

BROWSER

CHROME

0

1

0

1

0

1

0

1

0

COMPUTE

HTML/CSS/JS

HTML

WEB SERVER

BLUEHOST

PHP

gRPC

BACKEND SERVER

RASPBERRY PI 4B

GO (ON DOCKER)

GPIO

BREADBOARD

INTERCONNECTIONS

WIRES/RESISTORS

PMOD

FPGA DEV BOARD

ARTY S7-50
(SPARTAN FPGA)

VERILOG

THE MICROPROCESSOR ARCHITECTURE

Code written in verilog

Top-Level-Block-Diagram-of-the-8-bit-Microprocessor

Processor-Block-of-the-8-bit-Microprocessorr

THIS IS WHAT YOU ARE CONTROLLING

HEADER

JEFFRY A. DECOLA

CONTROL AN FPGA VIA A RASPI AND WEB SERVER

SECTION

CONTROL AN 8-BIT MICROPROCESSOR I DESIGNED

ARTICLE - HOME PAGE

THE MICROPROCESSOR ARCHITECTURE

THIS IS WHAT YOU ARE CONTROLLING